(1) Field of the Invention
This invention relates to a stacked gate flash memory cell structure and process which uses a large angle ion implant beam to form the source and drain regions in the cell. A low doped region is formed between the edge of either the source or drain and the edge of the first gate electrode. The tunnel dielectric is grown over this low doped region and is self-aligned with it. This method provides a self-aligned very small tunnel dielectric area.
(2) Description of Related Art
Conventional stacked gate flash memory cell structures have the disadvantage of a large tunnel dielectric area which requires large voltages for programming and erase operations of the memory cell. In addition larger tunnel dielectric areas introduce more defects and lower device yield. Often the tunnel dielectric is the same dielectric as the gate dielectric which leads to a compromise between gate dielectric thickness and tunnel oxide thickness.
This invention has the advantage of a tunnel dielectric which is independent of the gate dielectric and the thickness of each can be optimized. In this invention the tunnel dielectric is self-aligned to the source and gate and has a width that can be accurately controlled.